| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-4061 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40615
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 |
| filingDate |
2005-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3f4e86d363e44055375975948f98452
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f92e3ac8a9f9fb277438885211621c4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38931828a98d300def84b05efc619ef1 |
| publicationDate |
2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201440044-A |
| titleOfInvention |
Semiconductor memory device |
| abstract |
The trigger signal generating circuit (104) outputs a trigger signal. The delay circuit (110) accepts a trigger signal for outputting a delayed signal that delays the trigger signal. The clock counter (106) receives the clock, counts the number of received clocks from the time the trigger signal is received until the delay signal is received, and outputs the count result. The determination circuit (107) stores the correspondence between the number of clocks and the latency, and determines the latency corresponding to the count result output from the clock counter. The latency period uses the register (108) to maintain the latency determined. The WAIT control circuit (109) outputs the WAIT signal to the outside based on the latency held by the latency register (108). |
| priorityDate |
2004-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |