| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66825 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2013-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8cf2958c91ef6540badbceb602ff0d9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10ca4123ee48b0f034d149e527a3f3e6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d55c8ad4ce713ad1a6a8d7439164c6c2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c18b5dfd279df7e49e65a4779912c98
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_095be0b32557a0f21c5666e030733b0d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b772c040139703630da0a69f4f25e510
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef77cf20605abb62ff40ae1781b7aaed |
| publicationDate |
2014-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201434153-A |
| titleOfInvention |
Semiconductor device and method of manufacturing the same |
| abstract |
The semiconductor device of the present embodiment includes: a first element isolation region that partitions the semiconductor substrate into a plurality of first element regions; and a plurality of memory cells that are sequentially laminated with the tunnel insulating film on the first element region , a charge storage layer, an interelectrode insulating film, and a control gate electrode. Further, the semiconductor device includes: a second element isolation region that partitions the semiconductor substrate into a plurality of second element regions in a peripheral circuit region; and a peripheral transistor that sequentially builds gates on the second device region Polar insulating film, gate electrode. The first element isolation region includes a first element isolation insulating film embedded in a bottom portion of the first element isolation trench, and a gap formed between the first element isolation insulating film and the interelectrode insulating film, and the second element The isolation region includes a second element isolation insulating film embedded in the second element isolation trench. The film quality of the first element isolation insulating film is different from that of the second element isolation insulating film. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10424583-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I571967-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I797467-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10020310-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9735161-B2 |
| priorityDate |
2013-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |