http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201417245-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f823f036721e39c61ff0ced537273b8 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 |
| filingDate | 2013-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a7e34328f2d61f5de1443976eace28c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10334911250fd2d8dde90d0dbcf9193c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9db71e6ebedcc1c7b8a6232b14e0dbb7 |
| publicationDate | 2014-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201417245-A |
| titleOfInvention | Semiconductor structure and its forming method, SRAM storage unit, SRAM storage |
| abstract | A semiconductor structure and a method of forming the same, an SRAM memory cell, and an SRAM memory. a semiconductor structure comprising: at least two adjacent transistors formed on a semiconductor substrate; a gate of two adjacent transistors; a doped region between two adjacent transistor gates forming an opening; A conductive layer overlying the bottom and sidewalls of the opening. Another semiconductor structure includes: a first transistor and a second transistor formed on a semiconductor substrate; wherein the insulating layer of the gate of the first transistor covers only a portion of the gate electrode layer away from the second transistor doped region; The insulating layer, the gate electrode layer of the first transistor exposed by the insulating layer, the second transistor doped region, and the gate of the second transistor form an opening; and the conductive layer covers the bottom of the opening and the sidewall. The present invention also provides a method of forming the semiconductor structure, an SRAM memory cell including the semiconductor structure, and an SRAM memory. The present invention can reduce the area of the semiconductor structure. |
| priorityDate | 2012-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.