http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201417228-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-482 |
| filingDate | 2013-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d70c3ea6c36e17b55469fb070371e7e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f8a1f1c3d191eb655ae50bd20d8aec01 |
| publicationDate | 2014-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201417228-A |
| titleOfInvention | Semiconductor device |
| abstract | The present invention provides a semiconductor device. The semiconductor device includes a first MOS device layer stacking a second MOS device to form a first finger, and a drain of the first MOS device connecting a source of the second MOS device to form a first share a source/drain region; a third MOS device stacks a fourth MOS device to form a second finger, and a drain of the third MOS device is connected to a source of the fourth MOS device to form a second Two common source/drain regions, the first and second common source/drain regions are not electrically connected, the sources of the first and third MOS devices are interconnected; and the second and fourth MOS devices are germanium a gate interconnection; a gate interconnection of the first and third MOS devices; and gate interconnections of the second and fourth MOS devices. |
| priorityDate | 2012-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.