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filingDate 2012-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb1f29fdde8ed963abe40db51fe88021
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publicationDate 2013-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201336017-A
titleOfInvention Method for fabricating a semiconductor device having an isolated region of uniform ladder height
abstract A method of fabricating a semiconductor device is provided. In an embodiment, a method of fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and fills the trench with an isolation material. The spacer material is planarized to establish a top surface of the isolation material that is coplanar with the planarization stop layer. In the method, a dry slag removal process is performed to remove a portion of the planarization stop layer and a portion of the isolation material for lowering the top surface of the isolation material to a desired step height above the semiconductor substrate.
priorityDate 2012-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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