| abstract |
A chip package comprising: a substrate having a first surface and an opposite second surface, and a side connecting the first and second surfaces; a dielectric layer on the first surface of the substrate; and a plurality of conductive pads, including a conductive pad and a second conductive pad are disposed in the dielectric layer; a plurality of openings extending from the second surface of the substrate toward the first surface and respectively exposing corresponding conductive pads, wherein the first opening and the opening in the opening a second opening adjacent to the first opening, exposing the first conductive pad and the second conductive pad, respectively, extending in a direction crossing the side of the substrate beyond the first and second conductive pads; and the first circuit layer And the second circuit layer is located on the second surface of the substrate and extends into the first opening and the second opening to electrically contact the first and second conductive pads, respectively. |