| abstract |
The present invention relates to a wafer level package structure and a method of fabrication having an increased solder contact surface. First forming a first plastic sealing layer covering the front side of the wafer, grinding on the back side of the wafer, and then etching the through hole on the back side of the wafer, then filling the via hole with metal to form a bottom metal interconnect structure and on the wafer The back side is metallized to conduct the electrodes on the back side of the wafer to the front side of the wafer using the bottom metal interconnect structure. Cutting from the back side of the wafer forms a dicing trench that separates the wafer, and forms another second layer of plastic covering the backside of the wafer, grinding the thinned first molding layer to form a top molding layer on the front side of the wafer, and at the top A top metal interconnect structure is formed in the mold layer, and the top metal interconnect structure electrically connects the metal pads on the top mold layer to the electrodes on the front side of the wafer. The molding compound in the second plastic sealing layer and the cutting groove is then cut to separate a plurality of wafer level molding bodies. |