http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201243843-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00 |
| filingDate | 2012-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa07e0c99c24a951a9ae29a1ca0eb12f |
| publicationDate | 2012-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201243843-A |
| titleOfInvention | Memory circuit, memory unit, and signal processing circuit |
| abstract | A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I603621-B |
| priorityDate | 2011-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 73.