http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201227111-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6aa58e970d8541c69fca28fcac6e6993 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 |
| filingDate | 2010-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8cfbc39a156d5ff91d5bf41ed0390d9 |
| publicationDate | 2012-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201227111-A |
| titleOfInvention | Methods for manufacturing array substrates |
| abstract | Disclosed is a patterned photo resist layer on a passivation layer, formed by a lithography process with a multi tone mask, has a non-photo resist region, a thin photo resist pattern, and a thick photo resist pattern. The passivation layer corresponding to the non-photo resist region is removed, thereby forming vias to expose part of a drain electrode in a TFT and part of a top electrode in a storage capacitor, respectively. The thin photo resist pattern is then ashed to expose the passivation layer in a pixel region. Thereafter, a conductive layer is selectively deposited on the exposed passivation layer and on the sidewalls/bottoms of the vias. Subsequently, the remained thick photo resist pattern is ashed. |
| priorityDate | 2010-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.