| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06544
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-06 |
| filingDate |
2011-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f511ad90fce9a859d09b0bd6bab6563
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_318de44599fe4f1606eeeb9970d54d6c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e04902b019be7f7377aed7952f51eb49 |
| publicationDate |
2012-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201225101-A |
| titleOfInvention |
Semiconductor package and method of refreshing a stack of memory chips in the semiconductor package |
| abstract |
A semiconductor package and a method of refreshing a stack of memory chips in the semiconductor package are disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11334282-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I777487-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11194505-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11449453-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11681457-B2 |
| priorityDate |
2010-09-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |