http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201201360-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2010-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33742ab51ab614a3703a1f9a97c86694 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7a645a29927b05895c6d929640ed73af |
| publicationDate | 2012-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201201360-A |
| titleOfInvention | Nonvolatile memory device and manufacturing method thereof |
| abstract | A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the innerside wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I636551-B |
| priorityDate | 2010-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.