http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201105042-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_399a62424437cdee73e74a007502ec94 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0891 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-087 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-085 |
| filingDate | 2010-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c16d21801035afb51e040b511294091c |
| publicationDate | 2011-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201105042-A |
| titleOfInvention | Method and apparatus for generating an output clock with low clock jitter |
| abstract | A clock generator is disclosed, the clock generator comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; and a controllable oscillator to generate the output clock in accordance with a control by the control signal. |
| priorityDate | 2009-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.