http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201101395-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_213cf428c822780d4e1e4899315ec20f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-872 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66143 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-404 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0619 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8725 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-329 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-872 |
| filingDate | 2009-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb648bf141a3cb29bb93f8d51e88d0c3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63a27561de73f1b48adef9807005660e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7823427c0d44d3b5f1f597097072a5f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0856bcc8b67deb0ad9593128c2d53f21 |
| publicationDate | 2011-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-201101395-A |
| titleOfInvention | Trench Schottky diode and manufacturing mehtod thereof |
| abstract | The present invention relates to a trench Schottky diode and its manufacturing method. The method includes steps of: providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the semiconductor substrate through the first mask layer to form a multi-trench structure in the semiconductor substrate; forming a gate oxide layer on a surface of the multi-trench structure; forming a polysilicon structure on the gate oxide layer and the first mask layer; etching the polysilicon structure to expose a top surface and a portion of a lateral surface of the first mask layer; forming a second mask layer on a portion of the polysilicon structure and a portion of the first mask layer, and exposing portions of the semiconductor substrate, the polysilicon structure and the gate oxide layer; forming a metal sputtering layer on the second mask layer and the exposed portions of the semiconductor substrate, the polysilicon structure and the gate oxide layer; and etching the metal sputtering layer to expose a portion of a surface of the second mask layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I508309-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104112768-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9373728-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I578403-B |
| priorityDate | 2009-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 52.