| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bc905cbef116a1ec61d12125af9427f3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05569
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02377
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05001 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-525 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-04 |
| filingDate |
2009-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b96a91719436ca0d6fa77c28e7160c5f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1b9334b22f0166925b06c4390896d77 |
| publicationDate |
2010-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-201042272-A |
| titleOfInvention |
Method for repairing chip and stacked structure of chips |
| abstract |
A method for repairing chip with die-stacking structure is provided. First, a first chip includes a first circuit block having a first function, a second circuit block having a second function and a signal path electrically connected the first and the second circuit blocks. A second chip includes a third circuit block having the first function. A first and a second verification results are obtained by verifying the functions of the first and the second chips. The first block disables if the first verification result shows that the first block of the first chip is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the first verification result shows that the second block of the first chip is functional and the second verification result shows that the third block of the second chip is functional. |
| priorityDate |
2009-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |