http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-201034384-A

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0175
filingDate 2009-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_feaac678e94adbc19a9d7681ffee38b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6500a12f2ebaa26e1ad6e9bf58a08595
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publicationDate 2010-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-201034384-A
titleOfInvention Small area IO circuit
abstract A small area IO circuit is provided. The IO circuit has one or more parallel circuit unit(s) and an ESD protector installed between a core/pre-driver and an IO pad. Each circuit unit includes an off-chip driver and an output resistor, wherein the ESD protector protects ESD event occurred at the IO pad, and the resistor in each circuit unit acts as an ESD blocker to block ESD current from corresponding off-chip driver. Therefore, transistors in each off-chip driver do not have to be restricted by strict ESD design rules, such that at least a transistor of the off-chip driver(s) is implemented in a single finger layout to lower the equivalent capacitance of the off-chip driver(s), and layout areas of the off-chip driver(s) as well as the whole IO circuit can be reduced to achieve a small area IO circuit.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I799312-B
priorityDate 2009-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 24.