| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-458
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2009-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_429b44bc1eaf4f40992c9a144121eb4c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75c6267d8c775da162e94c833c3742ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b2671005bc7ce71dc85a1f4f9692e20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa07e0c99c24a951a9ae29a1ca0eb12f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e3fcf601d3c982647edb04227554ebd4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b3fe79e6f4f03704344434a8a4f530f7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78aa83dfb9454443017f3ff090b2314b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_067e88d90945e3d0bc037f8c04d0c97d |
| publicationDate |
2009-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200952180-A |
| titleOfInvention |
Thin film transistor and display device |
| abstract |
To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added. |
| priorityDate |
2008-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |