http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200939397-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cb5746eb832dced6146d31f543e23b29 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76256 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-868 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-16 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8229 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-102 |
| filingDate | 2008-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a421c4f0aabed509f490267fe8935b34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a0ee313c565249e97b3185769649c3f |
| publicationDate | 2009-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200939397-A |
| titleOfInvention | Vertical diode based memory cells having a lowered programming voltage and methods of forming the same |
| abstract | In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided. |
| priorityDate | 2007-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 75.