http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200919719-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2008-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8404b3333a5d2acad9c87fc1d1e28230 |
| publicationDate | 2009-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200919719-A |
| titleOfInvention | Semiconductor device having insulated gate field effect transistors and method of manufacturing the same |
| abstract | N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers. |
| priorityDate | 2007-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 68.