http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200910592-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f187eb8cb31e70d4acd428dd8beedd4f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-12 |
| filingDate | 2008-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_62deb67d60ad264f6adba43ba317b93e |
| publicationDate | 2009-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200910592-A |
| titleOfInvention | Semiconductor device |
| abstract | Provided is a semiconductor device which can reduce on-resistance by improving Hall mobility of a channel region. A trench gate type MOSFET (semiconductor device) (50) is provided with a p-type silicon substrate (1) whose crystal surface of a main surface is a (110) plane; an epitaxial layer (2) formed on the silicon substrate (1); a trench (3), which is formed on the epitaxial layer (2) and includes a side wall parallel to the thickness direction (Z direction ) of the silicon substrate (1); a gate electrode (5) formed in the trench (3) through a gate insulating film (4); an n-type channel region (2b) formed along the side wall of the trench (3); and a p-type source region (2c) and a p-type drain region (2a) which are formed to sandwich the channel region (2b) in the thickness direction (Z direction) of the silicon substrate (1). The trench (3) is formed the have the crystal surface of the side wall as a (110) plane. |
| priorityDate | 2007-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.