http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200901369-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_72ed91cb20a3ca510bb7e85d7fae504a
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
filingDate 2007-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bfa7dc2f99a552e71cf780126c6e34e4
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publicationDate 2009-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-200901369-A
titleOfInvention NAND-type non-volatile memory, source/drain line plug and method of manufacturing the same
abstract A method of a source/drain line plug is provided. A plurality of device isolation structures is formed in a substrate and an active area is defined between two device isolation structures. A source/drain region is formed in the substrate on the active area. A portion of the device isolation structure which disposed at the sides of the source/drain region is removed so as to a surface of the device isolation structure is lower than that of the substrate. A dielectric layer is formed on the substrate. After that, the dielectric layer is patterned to form a plurality of trenches to expose the source/drain regions. A selective silicon growth material layer at least covers the corner of the substrate of the active area is formed on the source/drain regions exposed by the trenches. A silicde layer and a metal layer are formed sequentially on the selective silicon growth material layer to fill the trenches so as to form a plurality of source/drain line plugs.
priorityDate 2007-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 27.