http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200849493-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f063b8222ec3c8e746a415e7f364473 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2007-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a4567175d6ad28210797cf7cb87022d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5522839a773b8830615ba26cf8ddfd21 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86cec680aecf31edf8a9ad72f12fe66f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed134b41592f011a5f9f116233b089af http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7562278e5977d7e1719f7eae36ba65b3 |
| publicationDate | 2008-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200849493-A |
| titleOfInvention | Method for fabricating non-volatile memory |
| abstract | A method for fabricating non-volatile memory is provided. A plurality of isolation structures is disposed in a substrate, and defines active areas. The isolation structures are arranged in parallel and protrude from the surface of the substrate. A plurality of mask layers is deposited on the substrate, and intersects with the isolation structures. The surface of the mask layers is higher than that of the isolation structures. A plurality of doped regions is formed in the substrate. A plurality of insulating layers is then deposited on the substrate between the adjacent mask layers. The insulating layers and the mask layers are with different etching selectivities. The mask layers are stripped away, and the substrate is exposed. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate in-between the isolation structures and the insulating layers. The floating gate is with a lower surface than that of the isolation structures. An inter-gate dielectric layer is further deposited on the substrate. A control gate is disposed between the adjacent insulating layers. |
| priorityDate | 2007-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.