| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d231147f38595bbe3114b758cba4a298
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2272 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-407 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4096 |
| filingDate |
2007-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e5b5bbeea40430c8617d7ff29fa986b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5840fc0f8ce7b9c20e1c9d8a47b6d663
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_847182ca6c410cf27d2fb0514614f6f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0c832b2747a984e746f6d6b081dea69
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cdf6e2c7fa34bb9891686a044074dc61 |
| publicationDate |
2008-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200842871-A |
| titleOfInvention |
Semiconductor memory device |
| abstract |
The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I419040-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I505089-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I689931-B |
| priorityDate |
2007-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |