| abstract |
The present invention discloses a super thin chip scale package structure and method of the same. The super thin chip scale package structure comprises a substrate, a wafer with a plurality of die having a plurality of bonding pads, a first dielectric layer, a via conductive layer, a second dielectric layer, a redistribution layer trace and soldering bumps formed on the wafer in sequence. Due to minimizing the sizes of the package structure, the present invention can provides a super thin chip scale package structure. Especially, the method for manufacturing the super thin chip scale package comprises sawing the wafer and back-lapping the back side of the wafer and etching the back side of the substrate to provide the super thin chip scale package structure. Accordingly, the present invention can minimize the size of the package structure, and improve the manufacturing process effectively. |