| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2007-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a52a3499743e50d7898691edd97b2b7a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ea75e01be5c8da3f304213f6a01adcf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_172006c4b0d42c5310709f79fe3fcd22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_02322c6590f46d6831adee74229a5ef0 |
| publicationDate |
2008-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200828519-A |
| titleOfInvention |
Memory cell and method for fabricating the same |
| abstract |
An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltage. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness. |
| priorityDate |
2006-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |