| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_af1df5447b0175bcbcbac4bad710daf7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3406
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-00 |
| filingDate |
2007-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d0a8d75db3c80ef9ebc1c85ce91eea80 |
| publicationDate |
2008-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200824121-A |
| titleOfInvention |
Method, IC and display system for power MOSFET integration |
| abstract |
A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I492385-B |
| priorityDate |
2006-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |