http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200822234-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28247 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2007-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7e9f6e1012eb8a49beccdb444193800 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6c0c4cbf701a03b3d8d8c39e6318f56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e45c9128a2ebb2960ba3bd490bb8b19b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6206e07b7f21898508847eaed11c98c6 |
| publicationDate | 2008-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200822234-A |
| titleOfInvention | Methods for forming semiconductor structures |
| abstract | A semiconductor structure comprises a PMOS device and an NMOS device. The PMOS device comprises a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate die1ectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device comprises a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer. |
| priorityDate | 2006-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.