http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200807413-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bc905cbef116a1ec61d12125af9427f3 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5634 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5645 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-063 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-062 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-15 |
| filingDate | 2006-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_135d833e47398d8f888ae16fb1733d1c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d16ec9c254e2c6e74e4d878c17e1851c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17ff65ce850a32cf579e36fe85e7245d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc87737bb430d3dc7722a3c98ed5c5cf |
| publicationDate | 2008-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200807413-A |
| titleOfInvention | Multiple state sense amplifier for memory architecture |
| abstract | The invention provides a multiple state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The memory cell has a variable resistance. The multiple state sense amplifier comprises: a source follower, coupled between the output terminal of the memory cell and an input node, for limiting the voltage of the output terminal of the memory cell to enable the memory cell to generate a memory cell current; a source follower circuit, coupled between the output terminals of the reference cells and a plurality of output nodes, for limiting the voltage of the output terminals of the reference cells to enable the reference cells to generate a plurality of reference currents; and a current mirror circuit, coupled to the input node and the output nodes, for generating a memory cell voltage on the input node according to the memory cell current and generating a plurality of reference voltages on the output nodes according to the reference currents. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I415132-B |
| priorityDate | 2006-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.