http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200532853-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2004-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c618b1e7d61abaf87b034cfbd217e060 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e45c9128a2ebb2960ba3bd490bb8b19b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_59efea53fad992ef4eb989469d63a758 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a00ce9d5a55c9464556bba6a4f12c24f |
| publicationDate | 2005-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200532853-A |
| titleOfInvention | Local stress control for CMOS performance enhancement |
| abstract | A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a stress type selected from the group consisting of tensile stress and compressive stress over the respective PMOS and NMOS device regions; removing a portion of the first dielectric layer overlaying one of the PMOS and NOMS deice regions; forming a second dielectric layer including a stress type opposite from the first dielectric layer stress type over the respective PMOS and NMOS device regions; and, removing a portion of the second dielectric layer overlaying one of the PMOS and NMOS device regions having an underlying first dielectric layer to form a compressive stress dielectric layer over the PMOS device region and a tensile stress dielectric layer over the NMOS device region. |
| priorityDate | 2004-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 54.