http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200525886-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_db711ec1d8404aced42586995037ce09 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0185 |
| filingDate | 2004-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10f146a9558871a8fdc96dfd7bfb0754 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b5cb7af325bd16c91bf657525e3c5c0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6500a12f2ebaa26e1ad6e9bf58a08595 |
| publicationDate | 2005-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200525886-A |
| titleOfInvention | Input/output buffer |
| abstract | An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad. |
| priorityDate | 2004-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 18.