http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200414407-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be7c61ad34e5c6b0c3d079ffb89e4139 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate | 2003-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_161009146f987ab4605b6244648cc4e3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a8e0b66ebb54788fd471e41041c6818 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7594443d473eded7ed103d0078d7b1f1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_db9b6bc9c9537746633fedebab6601ab http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_304cfa333e45672530f3e47541368da5 |
| publicationDate | 2004-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200414407-A |
| titleOfInvention | Method and device to increase the switching speed by changing the gate oxide structure of power transistor (2) |
| abstract | Method and device to increase the switching speed by changing the gate oxide structure of power transistor are introduced, especially a device able to increase the device switching speed. In a power transistor, an N- epi-layer .is formed on a silicon substrate. Make a gate oxide layer between the N- epi-layer and poly-silicon gate area, and then deposit a poly-silicon layer on the gate oxide layer to form a power transistor gate. It features are: the gate oxide layer is composed by same type top and bottom dielectric layers, where the area of the top dielectric layer is smaller than the bottom area to let the dielectric constant of the top dielectric layer is smaller than the bottom one. Therefore, the input capacitor (C=EA/d) is reduced and the rise time (Tr=2.2RC) is speeded to increase the device switching speed. In the meantime, the interface charges between the gate oxide layer and epi-layer are reduced and hence effectively achieve the insulated isolation among metal conductors. This invention changes the gate oxide layer of the power transistor. Since the dielectric constant is lowered, the capacitance is reduced, and then let the charges (Q=CV) accumulated below the gate oxide layer not so large to suppress the poor isolation problem of the oxide layer. The product reliability is raised. The production yield of high integrated semiconductor is also increased. |
| priorityDate | 2003-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.