| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_aa2177641c5a9e9b12f05e3eb33dc85f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04M1-725
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4234 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04M1-725
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 |
| filingDate |
2003-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ccd91ce2a098eefde648ac9e70acd6d4 |
| publicationDate |
2004-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200406705-A |
| titleOfInvention |
Application processors and memory architecture for wireless applications |
| abstract |
In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system. |
| priorityDate |
2002-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |