http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-200402111-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D5-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-123 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-321 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-18 |
| filingDate | 2003-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22c175e9482e387bfe3aa4c2eeeddbb1 |
| publicationDate | 2004-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-200402111-A |
| titleOfInvention | Method of forming a copper wiring in a semiconductor device |
| abstract | Disclosed is a method of forming a copper wiring in a semiconductor device. A copper barrier metal layer and a copper seed layer are sequentially formed along the surface of an interlayer insulating film including damascene patterns. In a state that a wafer is then loaded onto an electrical plating apparatus in which a copper plating solution is filled and a negative (-) power supply is also applied co the wafer, copper is plated to that the damascene patterns are sufficiently filled, thereby forming a copper layer. Next, the copper layer is polished in the plating solution by means of the electro-polishing process by changing the negative (-) power supply to the positive (+) power supply. Due to this, the surface of the copper layer is flat over the entire wafer. Thereafter, a chemical mechanical polishing process is performed until the surface of the interlayer insulating film is exposed, thereby forming copper wirings within the damascene patterns. As such, an uneven surface of the copper layer plated by the electroplating method is etched in the plating solution, thus making flat the surface of the copper layer and thin the thickness of the copper layer. It is thus possible to prevent a dishing phenomenon or an erosion phenomenon in a subsequent chemical mechanical polishing process. Therefore, the process margin of the chemical mechanical polishing process could be increased and process characteristics could be improved. |
| priorityDate | 2002-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.