| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66287 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 |
| filingDate |
2002-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a29effc9565a6b70b0bbfa436d7b1c8b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7bd5f5f415a2d472d0f04951fd8c7e7f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1a66955c727b781b6b2ec4efd488199
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8fb32c2ebf5717da5fd06be41b31e56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_816ba8249d31db24154ce19a55fc682e |
| publicationDate |
2003-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200308086-A |
| titleOfInvention |
Self aligned compact bipolar junction transistor layout, and method of making same |
| abstract |
The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer. |
| priorityDate |
2001-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |