| abstract |
A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under a metal connection pad. Using a low dielectric material such as air underlying the connection pad, pad capacitance is reduced, thereby improving the speed of associated electrical signal propagation. By configuring the structure to have pad supports at only a limited number of pad periphery points, a cured solder interconnection can absorb mechanical stresses associated with divergent movement between a semiconductor chip and a printed circuit board. Such a structure can be manufactured using the steps of: (1) depositing a soluble base material in an air cavity on an IC substrate, (2) depositing a metal pad layer on the soluble base layer, and (3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports. |