http://rdf.ncbi.nlm.nih.gov/pubchem/patent/SU-1450068-A1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2b15cc1d789a76a22333a3f5feae3e56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_13f5cd8b12ba2f7d0e07075f466a3fe2
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03B19-00
filingDate 1987-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1989-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_927e9c99a3bbd8dc1c766f4880aad5ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_03c7fa96a895ba770e9ad4cac90d4c40
publicationDate 1989-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber SU-1450068-A1
titleOfInvention Digital generator of sine signals
abstract The invention relates to radio engineering. The purpose of the invention is to increase the spectral purity of the decoded signals. The device contains the shaper 1 initial setup pulses, multiplexer 2, accumulating adders (NS) 3 and-4, multiplier 5, block 6 inverse signs, r-r 7 clock pulses, inverter 8, frequency code sensor 9, DAC 10 and filter 11 low frequencies. The signal for the initial value of the signals AQ through multiplexer 2, controlled by driver 1, is fed to the code input NA 3. At the output of NA 3, generic counts A. are formed, which are the values of the sinusoid rounded to the integer number. These values convert the DAC 10 to analog voltage, which through the filter 11, which smoothes the components at a clock frequency, enters the output of the device. The goal is achieved by the introduction of shaper 1, multiplex-cop 2, inversion block 6, IJAII 10, and filter 11. The device in clause 2 of the f-ly is characterized by the execution of multiplier 5, given its sludge. 1 hp f-ly, 2 ill. i (L
priorityDate 1987-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 19.