http://rdf.ncbi.nlm.nih.gov/pubchem/patent/RU-2769562-C1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_08d48226b9b7df66871401057f264708 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-52 |
| filingDate | 2021-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6c345aaa686ddc4ca0ba42ada41c8af |
| publicationDate | 2022-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | RU-2769562-C1 |
| titleOfInvention | Solid-state information storage controller decoder |
| abstract | FIELD: computer technology.SUBSTANCE: invention relates to computer technology and is intended to carry out the process of decoding digital information coming from several independent NAND flash memory chips in the controller equipment of non-mechanical storage devices based on NAND flash memory chips. A decoder of a solid-state data storage controller for decoding data from n NAND channels, containing a control unit that monitors the operation of the blocks included in the decoder, a channel controller consisting of n modules, each of which is connected to a specific NAND channel, a memory block for storing sectors containing independent memory modules, a decoder controller containing m decoder modules, where n>m, a decoder block containing m LDPC decoders, a unit for checksum calculation and data transfer to a recording unit and a unit for checksum calculation and data transfer to a host unit.EFFECT: increase in the efficiency of the technical storage medium due to the uniform distribution of the load of the NAND flash memory included in it during the read operation.9 cl, 1 dwg |
| priorityDate | 2021-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.