http://rdf.ncbi.nlm.nih.gov/pubchem/patent/RU-2176814-C2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-405 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4059 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29K23-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C08J9-232 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B32B27-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29C67-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B32B5-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B29C39-10 |
| filingDate | 1996-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6490aa7874fbb054c9895e32c5567b9b |
| publicationDate | 2001-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | RU-2176814-C2 |
| titleOfInvention | Circuit arrangement for reducing delay in transmitting buffer data between two one-to-one asynchronous buses |
| abstract | FIELD: computer systems; digital subsystems controlling data transmission between two synchronous buses. SUBSTANCE: first-to-second bus interface incorporates end circuit breaker of first bus that functions to control data transmission from first data bus to data buffer and end circuit breaker of second bus used to control data transmission from data buffer to second data bus. Respective valid-data flag is set for each storage location by end circuit breaker of first-bus interface when data are stored in storage location for data coming from first bus and cleared by end circuit breaker of second-bus interface when data are transmitted from storage location to second bus. For reducing time required for output of serial data from set of data storage locations in data buffer each data validity flag is synchronized independently. EFFECT: enhanced capacity of computer system. 5 cl, 5 dwg |
| priorityDate | 1995-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.