| abstract |
FIELD: digital computer engineering. SUBSTANCE: device having maximum detector, adder, source hypergraph incidence matrix recording bus, device input, first and second outputs of current arrangement estimation ties with outputs of maximum detector unit and adder, respectively, is provided in addition with storage unit, m identical circuit length counting units, where m is number of circuits, address bus, clear input, synchronization input, and end-of-exchange input with relevant ties. Device enables estimation of arrangement of single-sized elements in one-dimensional regular digital wiring space by two criteria: total length of circuits and maximum circuit length. EFFECT: simplified design, improved mean speed of device. 2 cl, 8 dwg |