http://rdf.ncbi.nlm.nih.gov/pubchem/patent/NZ-549359-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5b2d9a21d3754b7d870d70f81c995f8b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-45 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1608 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66863 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66068 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-8128 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0312 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-15 |
| filingDate | 2005-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e123ec4b31516fd224eb7a5e8fd9fb8a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e0e53c97e9b22985a38f29a733d6b5c2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f1fd9c6c4ce4d10c866cf91f2a6e22a9 |
| publicationDate | 2009-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | NZ-549359-A |
| titleOfInvention | Self-aligned silicon carbide semiconductor devices and methods of making the same |
| abstract | A method of making a semiconductor device comprises selectively etching a first layer of n-type SiC on a second layer of n-type SiC using a metal etch mask on the first layer of n-type SiC. The second layer of n-type SiC is less heavily doped with an n-type dopant than the first layer of n-type SiC. The second layer of n-type SiC is on a layer of p-type SiC which is on a SiC substrate layer and etching comprises etching through the first layer of n-type SiC and into the second layer of n-type SiC to form a plurality of discrete raised regions each having an upper surface. The plurality of discrete raised regions being spaced from one another thereby defining one or more recesses between adjacent raised regions. The one or more recesses have a bottom surface and sidewalls. The metal etch mask on the first layer of n-type SiC is annealed to form ohmic contacts on upper surfaces of the raised regions. One or more layers of dielectric material are deposited on exposed surfaces of the first and second layers of n-type SiC including the bottom surface and sidewalls of the one or more recesses. The method further comprises anisotropically etching through the one or more dielectric layers on the bottom of the one or more recesses to expose second layer- of n-type SiC; and depositing a Schottky metal on the exposed second layer of n-type SiC in the one or more recesses to form a gate junction. A semiconductor device made by the above method is also disclosed. |
| priorityDate | 2004-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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