http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-970052491-A

Outgoing Links

Predicate Object
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
filingDate 1995-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1997-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-970052491-A
titleOfInvention Dual gate manufacturing method of semiconductor device
abstract BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dual gate of a semiconductor device, wherein a gate oxide film is formed on a substrate in which active regions and field regions are defined, and an undoped polysilicon is deposited, and then, on one side The first impurity dope polysilicon layer is formed by implanting the first impurity ions, and the second impurity dope polysilicon layer is formed by implanting the second impurity ions into the undoped polysilicon layer on the other side. After forming a dual gate mask pattern on the dope polysilicon layer implanted with different dopants, the dope polysilicon layer is etched using the mask pattern to form dual gates (first gate and second gate). It consists of steps. In this case, in etching the polysilicon layers containing the different dopants, the concentration of the dopant is formed such that the polysilicon layers containing the different dopants form the same type of the first gate and the second gate. And the mixing ratios and concentrations of the constituents of the etchant.
priorityDate 1995-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 22.