http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20220081814-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_75d69b060cefcbb8e550fa1013ea0c5e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02B70-10 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0865 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate | 2020-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce8582fc23662090143319501f40dbdb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_87d1535b29d9456854e38b2a8a81c2c9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d3135cde9aa87a8dabf302bdfdc412f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a4ce60bf92cfcfb3ca19a2a2c72fedb8 |
| publicationDate | 2022-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20220081814-A |
| titleOfInvention | Power semiconductor device and method of fabricating the same |
| abstract | A power semiconductor device according to an aspect of the present invention includes a semiconductor layer of silicon carbide (SiC), a plurality of well regions disposed on the semiconductor layer and having a second conductivity type, and the semiconductor on the plurality of well regions A plurality of source regions each formed in a layer, each having a first conductivity type, from below the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions to provide a vertical movement path of charge A plurality of drift regions formed in the semiconductor layer to be connected and formed to be recessed into the semiconductor layer from the surface of the semiconductor layer to respectively connect adjacent two of the plurality of source regions to a drift region having a first conductivity type a gate electrode layer including trenches, a first portion filling the plurality of trenches, and a second portion on a surface of the semiconductor layer, corresponding to the first portion of the gate electrode layer, along the plurality of trenches a first channel region defined in the semiconductor layer to form an inversion channel, and a second channel region defined in the semiconductor layer to form an accumulation channel under the second portion of the gate electrode layer. |
| priorityDate | 2020-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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