| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41766
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2020-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9fc78cd4cdcab8780457a8e2c1486e0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e6160bae7376ec58441a4049d834e57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_646055d2206daff3361aa56d774cf51d |
| publicationDate |
2021-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20210153385-A |
| titleOfInvention |
Integrated circuit devices |
| abstract |
An integrated circuit device comprising: a substrate including a first fin-type active region and a second fin-type active region; a gate structure extending in a first direction parallel to a top surface of the substrate on the first fin-type active region and the second fin-type active region; a first source/drain region disposed on one side of the gate structure on the first fin-type active region; a second source/drain region disposed on one side of the gate structure on the second fin-type active region; a first source/drain contact disposed on the first source/drain region, the first source/drain contact including a first portion and a second portion, wherein an upper surface of the second portion is positioned at a level lower than an upper surface of the first portion; a second source/drain contact disposed on the second source/drain region, the second source/drain contact including a first portion and a second portion, wherein an upper surface of the second portion is positioned at a level lower than an upper surface of the first portion; a first stressor layer covering the top surface of the second portion of the first source/drain contact; and a second stressor layer covering the upper surface of the second portion of the second source/drain contact and comprising a material different from that of the first stressor layer. |
| priorityDate |
2020-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |