| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T2200-28 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-505
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30032
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30036
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T1-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T15-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06T17-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30021 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T15-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T15-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06T1-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-16 |
| filingDate |
2020-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e557fa262c1f8f9a9d648dbd0b82e166
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43086587ba406aa2c8ef27ac406b8704
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2bad4286db4824462d497cb2330e9b78 |
| publicationDate |
2021-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20210117911-A |
| titleOfInvention |
Apparatus and method for performing a stable and short latency sorting operation |
| abstract |
An apparatus and method for stable and low-latency alignment are presented. For example, one embodiment of the processor may include an input circuit that receives a set of N input values to be sorted in a sort order, and compares each input value in parallel with all other input values to obtain at least N * (N-1) /2 comparison circuitry to generate two comparison result values, and matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, wherein a plurality of bits in each row determine the result of the comparison with another input value. a first region of the result matrix storing a first set of bits containing N * (N-1)/2 comparison result values, wherein the first region of the result matrix opposite the first region contains a comparison result value representing Region 2 stores a second set of bits containing the inverse of N * (N-1)/2 comparison result values - and performs parallel addition of bits in each row to produce N unique result values It includes a parallel adder circuit that calculates and a sort circuit that returns a sort order by indexing with N unique result values. |
| priorityDate |
2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |