http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20210075486-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-157 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-155 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03H1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-158 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-0025 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M1-0064 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-087 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02M1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02M1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03H1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02M3-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-133 |
| filingDate | 2019-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c77a1c55818b421a38c711ca6b08ca8 |
| publicationDate | 2021-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20210075486-A |
| titleOfInvention | Clock distribution circuit using adjustable phase control and voltage converter including the same |
| abstract | The clock distribution circuit includes a phase locked loop, a first phase difference detection and conversion circuit, a second phase difference detection and conversion circuit, and a clock generation and compensation circuit. The phase locked loop generates a plurality of reference clock signals. The first phase difference detection and conversion circuit generates a plurality of input phase difference voltages by detecting a phase difference between two of the plurality of reference clock signals. The second phase difference detection and conversion circuit generates a plurality of output phase difference voltages by detecting a phase difference between two of the plurality of power switching signals received from the plurality of external switching regulators. The clock generation and compensation circuit generates a plurality of input clock signals provided to the plurality of external switching regulators by shifting the phases of the plurality of reference clock signals, and based on the plurality of input phase difference voltages and the plurality of output phase difference voltages The phase of at least one input clock signal is additionally adjusted. |
| priorityDate | 2019-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 63.