http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190112838-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2272 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-109 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 |
| filingDate | 2018-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9eb4bfe2e9bb7e73c520daeccfb630a2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dbdbeb4fc286a689f937bdc39b0fc1af |
| publicationDate | 2019-10-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20190112838-A |
| titleOfInvention | Apparatus and method for determining phase relationship between input clock signal and multiphase clock signal |
| abstract | An apparatus and method for determining a phase relationship between an input clock signal and a polyphase clock signal is disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals, and a timing for receiving a command, propagating the command through the command path in response to the internal clock signal, and reflecting the timing of the clock signal. And a command path configured to provide an internal command having. The example apparatus further includes a data clock path configured to receive the data clock signal, provide multiphase clock signals based on the data clock signal, and provide a delayed polyphase clock signal, receive a delayed polyphase clock signal and respond to an internal command. And further comprises a clock synchronization circuit configured to latch the logic level of the delayed polyphase clock signal. |
| priorityDate | 2017-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 |
Total number of triples: 20.