| abstract |
The power consumption of the semiconductor device is reduced efficiently. The semiconductor device has a power management device, a cell array, and peripheral circuits for driving the cell array. The cell array has a backup circuit for backing up data of word lines, bit line pairs, memory cells, and memory cells. Row circuits and column circuits are provided in the power gateable first power domain, and the cell array is provided in the power gateable second power domain. In the operation mode of the storage device, a plurality of low power consumption modes having lower power consumption than the standby mode are set. The power management device selects one of the plurality of low power consumption modes and performs control for the memory device to transition to the selected low power consumption mode. |