| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-065 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 |
| filingDate |
2018-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_07149c137f8fa5f6d1167f1e7ddf95f5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bba304ccae76d325accebe8460b5684c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c361e919a939e9f72e30c4852b72c439 |
| publicationDate |
2019-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20190084498-A |
| titleOfInvention |
Semiconductor device |
| abstract |
A semiconductor device according to an embodiment of the present invention includes: a plurality of memory banks arranged in a first direction; An address decoder disposed on one side of the plurality of memory banks; A plurality of local sense amplifier arrays disposed under each memory bank; A plurality of first input / output lines connecting the plurality of memory banks and a local sense amplifier array corresponding to each memory bank; And at least one second input / output line connected to the plurality of local sense amplifier arrays and extending in the first direction. |
| priorityDate |
2018-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |