| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1211
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-845 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2017-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34092550cc771f2eb8c2a0911c977a8f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_048ba184dcf89d019be96486158ce24a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b325a56a1d6ef1044d7603a012b40aed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_029f5388b1112e6eb71356ea45446b05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3fa27817f49b23813f64f4a25a2d5d93 |
| publicationDate |
2019-03-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20190024534-A |
| titleOfInvention |
Self-aligned structure for semiconductor devices |
| abstract |
This disclosure relates to semiconductor devices and methods of manufacture, and more particularly to semiconductor devices having self-aligned isolation structures. The present disclosure provides self-aligned spacing pins that can be formed by depositing a dielectric material in an opening formed in the spacing layer or by replacing a portion of the fin with a dielectric material. The self-aligned isolation pins may be separated from each other by a critical dimension of the photolithographic process used. The separation between the self-aligned isolation pins or between the self-aligned isolation pin and the active pin may be approximately equal to or greater than the separation between the active pins. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11735647-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11038058-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11038061-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11664454-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20210122676-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20210152920-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200125896-A |
| priorityDate |
2017-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |