| abstract |
The memory module includes a memory device, a command / address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input / output terminals for receiving first command / address bits, and a second set of input / output terminals for receiving data bits and second command / address bits. The command / address buffering device outputs first command / address bits to the first set of input / output terminals. The processing data buffer outputs data bits and second command / address bits to the second set of input / output terminals. The memory device is configured such that the first command / address bits, the second command / address bits, and the data bits are all used to access the memory cell array. Accordingly, the memory module according to embodiments of the present invention can be connected to a memory channel according to a memory module standard, and can be implemented in a processing in memory (PIM) structure without structural modification of the memory device. |