http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20170097006-A

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publicationDate 2017-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20170097006-A
titleOfInvention Optimizing gate profile for performance and gate fill
abstract Systems and methods for optimizing gate profiles for performance and gate charging are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending over the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of the channel region. The gate stack is disposed over the channel region, and the gate stack includes a top portion that is separated from the bottom portion by a tapered portion. At least a portion of the top portion and the tapered portion is disposed on the pin.
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